Memory packaging arrangements for high speed computers and other devices include a plurality of memory module sockets mounted on a printed circuit board and coupled to a module bus that is printed thereon. For example, U.S. Pat. No. 5,530,623 (Sanwo et al.), issued on Jun. 25, 1996, discloses a high speed memory packaging scheme comprising a plurality of memory module connectors mounted on a printed circuit board and interconnected by a plurality of transmission lines forming a bus on the printed circuit board. Each of the transmission lines sequentially connects respective points on the plurality of connectors which are connected in a same sequence by each of the transmission lines. Each connector is designed to receive a memory module, such as a Single In-line Memory Module (SIMM), and provides electrical connections between the plurality of transmission lines and memory logic within a memory module that is coupled to the connector. Each connector further provides an open circuit in each of the transmission lines in the absence of a memory module being coupled to the connector. Therefore, in one embodiment, a termination module including termination resistors corresponding to the plurality of transmission lines is provided for installation into the connector immediately following the connector(s) into which memory modules are installed. Still further, discrete termination resistors are provided in the printed circuit board at the end of predetermined ones of the transmission lines adjacent the last connector so that all connectors can be utilized.
Referring now to FIG. 1, there is shown a Dual Inline Memory Module (DIMM) 10 (shown within a dashed line rectangle) which corresponds to an arrangement for a Synchronous Link Dynamic Random Access Memory (SLDRAM) type of buffered module as recently proposed by the SLDRAM Consortium for such memory modules. The DIMM 10 comprises a printed circuit board 12 comprising a connector 14 mounted on one end thereof, a module bus 16 comprising a plurality of parallel conductors (not shown) coupled at first ends thereof to predetermined terminals (not shown) of the connector 14, a buffer chip 18 coupled to predetermined conductors of the module bus 16, a plurality of DRAM memory modules 20 (of which eight modules 20 are shown) coupled to the module bus 16, and a terminating resistor device (TERM. RESIS.) 22 coupled to second ends of predetermined conductors of the module bus 16 adjacent to the last DRAM memory module 20 location along the module bus 16. The connector 14 is used to connect the printed circuit board 12 to a much larger integrated circuit board (not shown), while the buffer chip 18 provides appropriate buffering for signals propagating along the module bus 16 between the circuits on the larger integrated circuit board and the memory modules 20. This is similar to the arrangement disclosed in FIG. 3 of U.S. Pat. No. 5,530,623, cited hereinbefore. The arrangement of FIG. 1 has been found to have severe signaling problems caused by reflections and/or crosstalk along a module bus 16. More particularly, the electrical conductors of the module bus 16 are not terminated with the proper impedance (Z.sub.0) of these transmission lines, but are instead a lesser impedance value in order to increase the speed of the DIMM. It is found that under such condition, when reading from the eighth or last memory module 20 along the module bus 16, the specified values for the high and low output voltages cannot be satisfied.
It is desirable to provide an arrangement which permits the module bus 16 to be terminated with appropriate resistances to overcome the problem found in prior art arrangements, while permitting the memory modules 20 to be mounted along the module bus 16 to operate at a high speed.